Fiesta® Process Tools

Comit's Fiesta® is an integrated set of tools with a vision to painlessly transform specifications to product, by producing as much of code and documentation automatically as possible, and simultaneously setting up a compatible verification environment from the start. Designers, therefore, are free to focus on designing state machines and creating tests. Coexists with industry standard EDA tools for simulation, synthesis and layout.

The Fiesta® toolkit addresses key design issues such as Design Entry, Change Management, Design Verification to get your designs up and running early with a high confidence level.

Fiesta® Installation Modes:

• Standalone Tool Mode
• Integrated Toolkit Mode
  

Standalone Mode: The following Fiesta® process Acceleration Tools can be purchased and used in standalone mode:

• Fiesta® CACT Architecture capture Tool
  • Accepts block level architectural input including third party IP and generates implementation roadmap by defining placeholders for all modules and interfaces
• Fiesta® CWGT Waveform & Constraints Generation Tool
  • Produces output signal waveforms based on a GUI based input of signals and their transitions
• Fiesta® CRST Register Specification Tool
  
  • Accepts register bank definitions for a chip. Generates and regenerates documentation, software interface definitions, hardware implementations and verification definitions, preserving consistency, and avoiding errors
• Fiesta® CSMT Finite State Machine Editor
  • Generates synthesizable Verilog code, and diagrams for documentation from state machines
• Fiesta® CVXT Open Verification Environment
  • Provides the ability to build parallel, automated, synchronized, self-checking verification testbenches for complex ASIC, SoC and programmable SoC designs. The environment bolts on to industry standard Verilog simulators and supports both real-world system testing and rigorous hardware module level and interface tests
    
• Fiesta® CMMT Simulation Memory Modeler
  • Generates dynamically configurable simulation time memory models that can be used in advanced system-level verification
• Fiesta® CSGT Synthesis Script Generation Tool
  • Accepts constraints and generates script to automate synthesis flow for popular synthesis tools
• Fiesta® CMBT Memory BIST Controller
  • Memory BIST controller with full-speed testing and automatic fuse-map generartion for laser repair stations
• Fiesta® CAVT AHDL to VHDL Conversion tool
  • Converts Altera's proprietary HDL - AHDL to portable VHDL files to target any technology

Integrated Toolkit Mode: The Fiesta® Process Standardization & Acceleration Toolkit is also available as a set of integrated tools where the output of one tool forms the input of another tool in the chain. Click here for an Overview of the Integrated Fiesta Process Standardization & Acceleration Toolkit.

 

    Industrial-strength
    toolkit proven at Comit
    Contract Engineering
    Center

    Installs in standalone
    or integrated mode

    Jump-starts design and
    verification cycles

    Addresses key design
    issues:
    - Architecture layout
    - Controlled Design Entry
    - Automatic Code       Generation
    - Automatic Change       Management
    - Integrated Verification
    - Automatic Documentation

    Supports multi-million
    gate complex SoCs

    Coexists with Industry
    Standard EDA tools

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