JISP Player / Encoder
Cool tool to perform In-Systems-Programming from remote host over IP, Network, Phone or serial connection, using JTAG

Verilog-Tcl Bridge
Integration of tcl into the simulation / verification environment Benefits include observing graphical output during Verilog Simulation, instead of just waveforms. The free download is single threaded. Comit would be happy to discuss applying the multi-threaded version for your immediate SoC verification needs.

Automated Incremental Save in Verilog-XL*
Saving frequent value-change dumps during simulation is invaluable in tracking down errors, if it can be done without slowing down the simulation too much, running out of disk space, or excessive monitoring

Comit TX : Verilog Testbench Extraction Tool
Speeds up the design process by saving time in module level verification. Extracts a self-checking Verilog testbench of any module inside a design that has a system level testbench, and with the extracted testbench, enables the module's replacement to be verified in a stand-alone basis in an environment identical to its final working environment, without having to simulate the entire system

mempkg : VHDLMemory Management Package
Simple linked list based Create on Demand memory package that allows modeling of large memories without statically allocating memory resources on verification host