Automated SoC Verification Environment

The Challenge
Designing and implementing a replicatable verification environment that provides the ability to efficiently write and run automated parallel, synchronized, self checking tests for complex SoC designs.

The Solution
Comit built a Complete SoC Verification Environment, described in the figure below.

At the core of the automated environment is a multi threaded Verilog Simulator-tcl Interpreter interface. The environment allows each interface (or feature) to be tested in parallel with other interfaces. All interface tests run simultaneously; each in its own tcl interpreter.

Each thread can interact with the design under test (DUT) running inside an industry standard Verilog simulator. The tests can create stimuli, automatically wait for events and triggers from other interfaces and observe and log results by interacting closely with the interface-only test bench and instrumented models.

The environment synchronizes threads with each other and with the simulator, and provides a highly automated environment for conveniently writing and running self checking tests.

Comit's SoC verification services currently use this automated SoC Verification Environment. The Verification environment is currently available on Solaris (7 & 8) and Linux (Redhat 7.1).


Verilog® is a registered trademark of Cadence Design Systems, Inc.

  Full Verifn. Environment

  Handles Self checking tests

  Complex SoC Designs

  Parallel synchronized tests

  Supports industry standard
  Verilog simulators

  Fully automated

 

FIESTA CVXT SOC
VERIFICATION
ENVIRONMENT