Comit-TX™ The Verilog Testbench Extractor
Comit-TX, is an innovative Verilog Test Bench Extractor that speeds up the design process by saving time in module level verification.
With increasingly large and complex designs, different modules tend to be represented at different levels of abstraction in the initial phases of the design. They would later be replaced by RTL or structural representation.
Even then, the modules continue to be modified for a variety of reasons, including area or timing optimizations. While modifying the different modules and fitting them back into the full design, it is critical to ensure that the module's functionality and its interface with other modules remain unchanged.
Verifying the different modules in a design by simulating the entire system is time consuming.
Comit-TX extracts a self-checking Verilog testbench of any module inside a design that has a system level testbench. Comit-TX, with the extracted testbench, enables the module's replacement to be verified in a stand-alone basis in an environment identical to its final working environment, without having to simulate the entire system.
During simulation, the extracted testbench applies vectors on the input signals of the module and monitors the output signals for expected behavior. As the testbench is self-checking, the verification is automatically done during simulation, and a report is produced indicating any mismatch between the expected and observed behavior of the module.
System Requirements
1. Cadence Verilog version 2.5 or higher
2. SunOS/Solaris 5.5 or higher
3. Perl 5.0The Comit Test Bench Extractor is a tar file which has all required files and documentation required to effectively use it. Take a look at the user manual before you download the file.