has taped out multi million gate ASICs with multiple
clock domains. Recent designs are targeted to cutting
edge 130nm processes in Low Voltage Fluro-Silicate-Glass
and LV OD.
knowledge of front-end RTL design as well as back-end physical layout
ensures tight coupling in concurrent RTL physical design strategies.
Comit's experience in multi-million gate hierarchical design with industry
standard design tools ensures early management of pitfalls such as channel
routing and horizon effects.
with a gate level netlist handoff, generate and insert:
- TAP Controllers
- Boundary scan
- IOLIOH vectors
- DC parametrics
- Connectivity tests for multiple dies in a package
Generate ASIC top level including
- I/O Muxes
- Pad ring
Generate Scripts for
- die layout tools
- packaging and test tools
- Power & Ground Strap generation and placement
- Automatic & Manual I/O Placement
- Clock tree synthesis
- Place & Route
- Parasitic extraction
- Timing closure
experience with a variety of silicon vendors virtually guarantees your
designs will work first time. Comit has targeted designs to Agere,
Lucent, NEC, OKI,
TSMC and UMC. Familiarity with silicon vendor process
design kits and third-party libraries, and knowledge of foundry
sign off parameters including foundry-preferred layer mapping
tables and verification grids, metal coverage rule
and antenna rule checks, and knowledge of specific process parameters
relating to RC extraction etc. minimizes your risk, and has contributed
to Comit's unbroken record of first silicon success.
of Reticle Enhancement Techniques (RET) such as optical and process
correction, phase-shift mask, scattering bars and off-axis illumination
ensures that Comit can work with your silicon vendor on physical verification
of sub-wavelength designs.