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Comit HomeASIC design

At Comit the goal of design flow is first-time working silicon.

Our engineers invest significant effort in refining processes and flows to ensure that goal. They define design guidelines and formulate documentation standards to ensure that your project execution is both professional and consistent.

Design Flow

  • Study Phase
  • Functional Design
  • Functional Verification
  • Synthesis
  • Pre-layout Verification
  • Test Synthesis
  • Floor Planning
  • Place and Route
  • Post-Layout Verification
  • ATPG Test Vector Generation
  • Tapeout

Comit would be happy to make a detailed design flow presentation covering Specifications to Tapeout at your office, on request.


Tools Used

  • Simulation/Verification
  • Cadence Verilog XL™
    Modeltech ModelSim™
    NC Verilog™

  • Synthesis

Synopsys: Design Compiler Ultra™
Synplicity: SynplifyPro™
Exemplar: Leonardo™
Synopsys FPGA Express™

  • Test / Timing Analysis

    Synopsys Test Compiler™
    Prime Time™
    Tetramax™
    Motive™

  • Formal Verification

    Verplex Conformal™

  • Backend tools

    SoC Encounter
    Nanoroute™
    Calibre™
    Fire&ICE™

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